Video controller

Video streaming into video walls is usually performed by a video controller, which buffers a video stream from common video technologies such as HDMI or DisplayPort in a frame buffer and streams it from there into the video wall via Ethernet.

For such a video controller we developed for an SoC the FPGA design, the Embedded Linux based on Yocto, several Linux driver and a Linux userspace application.

Our services

  • Concept and implementation of the FPGA design.
  • Concept and implementation of the lower software stack like Linux drivers and user space application
  • Setting up the Yocto environment for the Arria10 based SoM

Conceptual design and development of DMA engine

  • Linux
    • Driver for DMA management and configuration
  • FPGA
    • AXI-Master for DMA read and write transfer
    • Channel mapper to map multiple DMA channel to multiple AXI-Master
    • Load balancer for mapping DMA channel

Conceptual design and development of GUI video output

  • Linux
    • Framebuffer driver used by X11 and console
  • FPGA
    • HVSync generator for VESA signal generation
    • Connection to DMA engine for down stream
    • Connection to DisplayPort ipCore from Bitec for output stream

Conceptual design and development of DDR memory transfer controller

  • FPGA Memory transfer controller for parallel read and write accesses, optimized to reach maximum possible memory data rates

Conceptual design and development of video input

  • Linux
    • Userspace program for configuration
    • Driver for configuration and status register access via AXI-Lite
    • Driver for feeding video preview to the Linux v4l subsystem
  • FPGA
    • Memory write barrel-shifter for framebuffer pixel map compression for different color depth
    • Connection to DisplayPort ipCore from Bitec for input stream
    • Connection to memory transfer controller for write stream
    • Preview extractor for preview
    • Video Test pattern generator (TPG)

Conceptual design and development of ethernet output

  • Linux
    • Userspace program for configuration
    • Driver for configuration and status register access via AXI-Lite
    • Driver to map up to 16 Ethernet ports into the Linux network subsystem
  • FPGA
    • Stream controller, requesting video data segments from memory transfer controller
    • Ethernet encoder to generate UDP video packets
    • Demultiplexer to split ethernet video packet  stream when using multiple 1G-Ethernet
    • Packet multiplexer to multiplex Ethernet data from Processor and the ethernet encoder
    • Connection to 10G-Ethernet-MAC ipCore from Intel/Altera
    • Connection to 1G-Ethernet-MAC ipCores from Customer
    • Connection to DMA engine for ethernet packet down stream

Conceptual design and development of ethernet input

  • Linux
    • Driver to map up to 16 Ethernet ports into the Linux network subsystem
  • FPGA
    • Input layer 4 packet filter
    • Connection to 10G-Ethernet-MAC ipCore from Intel/Altera
    • Connection to 1G-Ethernet-MAC ipCores from Customer
    • Connection to DMA engine for ethernet packet upstream

DisplayPort ipCore Firmware

  • NIOS II
    • Bringup firmware example from Bitec and adapt it to the own requirements
  • Linux
    • Porting the NIOS II firmware to a linux driver
  • FPGA
    • Instantiating NIOS II softcore processor and connect to own logic design

Used technologies

Technologies

  • Embedded Linux
  • Embedded Linux driver
  • Linux v4l
  • Linux framebuffer
  • Devicetree
  • Linux kernel
  • Linux driver
  • u-boot
  • C/C++ programming language
  • VHDL programming language
  • AXI-Lite, AXI-DMA
  • DDR4 memory (Intel-EMIF)
  • Bitec DisplayPort ipCore

SoMs

  • Arria 10-SoM from Dreamchip

Interfaces

  • SPI
  • 1G-Ethernet
  • 10G-Ethernet
  • DisplayPort
  • USB
  • RGMII

Used tools

Software development

  • kdevelop - C/C++ development IDE for developing Linux drivers and Linux userspace programs
  • Yocto - building the embedded Linux images
  • NIOS II embedded design suite - C/C++ development IDE for developing software for the NIOS II softcore processor

FPGA design

  • Quartus from Intel/Altera - FPGA development
  • TimeQuest from Intel/Altera - FPGA timing analysis
  • SignalTap logic analyzer - FPGA logic analyzer for real time analysis
  • GHDL - FPGA simulation
  • Modelsim - FPGA simulation

Revision and project management

  • Git - version control software
  • Gitlab - version control and ticket management software

Documentation

  • Doxygen - VHDL and C/C++ source code documentation