Used core technologies in FPGAs and SoCs

RPMSG - Remote Processor Messaging is a virtio-based messaging bus that allows processors to communicate with remote processors available on the system.

We used it on an i.MX8-SoC to communicate from a Linux driver running on the A53 cores with a bare metal program running on the M4 coprocessor.

AXI is an "Advanced eXtensible Interface Bus" of the Advanced Microcontroller Bus Architecture (AMBA). It is used to

• connect ARM processors to their peripherals
• interconnect Xilinx and Intel/Altera ipCores

We have developed an AXI-Lite slave core and an AXI master core, which we use to connect our logic to these buses.

These modules are used on Xilinx Zynq SoCs, Intel SoCs and PCIe systems.

A clock management is part of every FPGA.

We have experience with DLLs, PLLs, Fractional PLLs, with fixed frequencies but also with dynamically adjusted frequencies and phases, on Xilinx, Altera/Intel and Lattice FPGAs.

We are experts in clock domain crossing techniques and have been using these techniques successfully for years.

DDR-SDRAM is a low-cost, dynamic RAM memory.

We have acquired experience with DDR memory in the course of several projects. The connection to the FPGA was done via
the Memory interface generator (MIG) from Xilinx in the Vivado as well as via the the Enhanced Memory Interface (EMIF) from Altera/Intel.

In all projects, the aim was to optimize the memory accesses by making the best possible use of the controller command depth and parallelism, taking into account the refresh rates of 7.8 us and 3.9 us, in order to achieve the maximum possible data transfer rate.

DisplayPort (DP) is a connection standard standardized by VESA for the transmission of digital image and sound signals.

We have collected experience with the DisplayPort core from Altera and Bitec on an Altera/Intel Arria10 SoC. Both DP input and DP output were operated with resolutions from 640 x 480 pixels to 3840 x 2160 pixels.

We have revised the Bitec configuration controller and extended it to two DP ports with gigabit transceiver lanes located into one bank, sharing the same avalon configuration bus.

Ethernet is a transmission technology that enables data transmission on different layers.

Therefore, our experience with Ethernet in FPGA is also very versatile. We have

• 100 MBit Ethernet used for an FPGA intercommunication by using the physical layer (MII interface) directly with a custom protocol
• Used tripple-speed Ethernet with UDP protocol by generating UDP packets in the FPGA and writing them to an SFP module (fiber and copper) via an Altera PCS core.
• 10 GBit Ethernet with UDP protocol by generating UDP packets in the FPGA and writing them to an SFP module (fiber) via the Altera MAC core.

An Ethernet switch represents a coupling unit between several Ethernet network sements.

For an Altera/Intel Arria10 SoC, we designed a Level 3 switch with IP/ARP/UDP filtering capabilities to allow shared access from the processor and FPGA to up to 16 Ethernet strands and to offload incoming packets from the processor.

A frame buffer is an image memory which is directly written to for graphics output.

As part of projects, we have implemented our own framebuffer on a CycloneV SoC and an Arria10 Soc. The implementation consisted of a Linux driver in the HPS and a DMA mechanism as well as a VSync-HSync signal generator in the FPGA. The image was output on a VGA output and a DisplayPort output, respectively.

A Gigabit transceiver in the FPGA is used to convert a parallel data stream into a fast serial data stream. This is usually 8b10b coded. The building blocks of a Gigabit transceiver are the PMA (physical medium attachment) and the PCS (physical coding sublayer).

We have been able to gain experience with a direct-use Gigabit transceiver for Ethernet as well as for the development of a fiber optic extender. Parts of the project scopes were:

• Development of a Link-State-Machine (LSM)
• A multiplexer mechanism for three channels (USB, I2C and Ethernet)
• Development of an error protection coding
• Sending of UDP packets encoded in the FPGA

PCI is a "Peripheral Component Interconnect" bus, which has found wide use in almost all industries. It allows the mapping of memory areas of the hardware into the general memory address space and the direct access (DMA) from the hardware into the working memory.

We have already realized several projects using PCI or PCIe on Xilinx FPGAs:

• Configuration of the FPGA via registers addressed via BARs
• Data transfer of measurement data via several DMA channels
• Integration of the FPGA into Linux systems via an own PCI driver

Currently we use the PCI-ipCore from Xilinx and use the AXI interface of the ipCore to connect the FPGA logic to the ipCore with our own AXI-Lite and AXI-Master modules mentioned above.

A softcore processor is the interconnection of FPGA logic to a processor, which in turn runs software. We have experience with the

• Xilinx PicoBlaze processor, for which we offer a development environment and which we use in many applications in a resource-saving way.
• Altera/Intel NIOS2 processor, with which we controlled and monitored a DisplayPort core

I2C stands for Inter-Integrated-Circuit and is a bus which is mostly used for the slower inter-chip communication with 100 kBd or 400 kBd.

We have already implemented several implementations of the I2C bus in the FPGA, from a pure I2C monitor to an I2C master to an I2C slave.

SPI is a serial peripheral interface, which is often used in interchip communication. The SPI protocol is very versatile in terms of data transmission. However, since only one method is needed per chip, the implementation is done so easily and quickly that we connect each chip individually with its requirements.

We have already implemented well over 30 SPI interfaces.

UART is a universal asynchronous protocol for bidirectional data transmission. It is one of the most widely used protocols. Almost every microcontroller has one to several UART interfaces, there are bridges from UART into newer technologies like USB.

We use UART very often for low baud rate communications up to 3 MBaud between FPGA and PC. For communications between two FPGAs, we have had it operating stably at 16 MBaud with a transmission distance of 100 m.

A UART interface is quickly written in VHDL, so it is not necessary to use ipCores from other manufacturers. We have several UART implementations with fixed and adjustable baud rate.

VGA is a computer graphics standard that allows analog driving of image sinks.

We have implemented a VGA output in the FPGA as part of a project.