FIDEx errata

We test Fidex very thoroughly before we issue a new release. However, it may happen that errors remain. We are trying to fix all remaining errors in a timely manner, if they are critical or there is no workaround.

Unfixed

Currently no known issues.

Fix for your system

Can not find online-help on some Linux systems

During startup FIDEx shows the message that FIDEx can not find the online help.

Solution: FIDEx depends on libqt4-help and libqt4-help depends on libqt4-sql-sqlite but libqt4-sql-sqlite is not installed on your system. Please make sure that all outer dependencies of the packages needed by FIDEx are installed on your system.

Fixed in FIDEx

Can not open import filter files

During opening the import filter dialog, FIDEx searches the asmImportFilter directory of its installation environment and tries to read all found import filter files.

On Linux systems this goes wrong, because FIDEx tries to open the files with read/write access but the files are installed without read permission.

Workaround: Give read/write access to all files below the asmImportFilter folder.

Fixed in 2016-09.0, comming soon.

Assembler ignores ioDevices defined by assembler directive

Workaround: Output files defined by gui are working.

Fixed in 2016-01.1

Broken link on "Getting started" page to "Processor manuals" page.

Fixed in 2016-01.0

FIDEx crashes trying unsupported "*register", "&register" and negative numerics

Fixed in 2016-01.0

ret instruction affects the zero and carry flags in all Simulators

Fixed in 2014-03.0

Xilinx PicoBlaze 3 simulator crashes after pressing reset button

Fixed in 2014-03.0

addC and subC instruction in Xilinx PicoBlaze 6 simulator

Fixed in 2014-03.0

The Zero flag is set wrong by simulating the addC and subC instructions within the PicoBlaze 6 simulator.

Workaround: Correct the zero flag manually in the simulator by clicking on it.

Verilog output files: Invalid entity name in verilog output files

Fixed in 2014-09.0

During writing verilog output files by modifying verilog template files the {name} tag is not replaced correctly with the entity name.

Workaround: Use the VHDL output file instead with your verilog template file and your verilog entity name. The VHDL and verilog output file generation mechanisms are equivalent.

Online help: Wrong argument order description for EQU directives in chapter "EQU directive", section "Renaming hardware components"

Fixed in 2014-07.2

The order of the arguments must be:

#EQU yourRegName, s0
#EQU yourRegBankName, A

s0 is the name of a Xilinx PicoBlaze register and A is the name of a Xilinx PicoBlaze register bank.

Assembler and Online help: Little and big endianess swapped

Fixed in 2014-07.1

The Endianess swapped by mistake. All numerics are internally stored in little endianess format, not in big endianess format. 

Workaround: To convert a little endian numeric to big endian please use 'LE attribute as workaround.